I last left off with the makings of an address decoder using a pair of 74hc595 serial to parallel shift registers. I added some LED indicators to the address bus so I can see the activity as I cycled through.
Understand that I am primarily a developer, electronics comes naturally to me, but proficiency comes with experience so forgive any of my “worst practices” that might make an electrical engineer cringe.
This time around I had an old 64kb static ram chip. It was from an old PC secondary cache which were used in banks of 4. I also added LED indicators to the data bus. The main reason was to see if the address bus was iterating through cells in the RAM chip properly. Most memory initializes with alternate pages as all zeroes and either a random or fixed pattern. This allows you to check the ram for bit errors. This worked for me because I tied the enable output line to the clock.
The one thing I was stuck on was the data bus. I didn’t want to use 8 pins for I/O on the Arduino Nano I was testing with. Everything I read was using two shift registers for the data bus. Then I remembered I has a bunch of 74HC299 universal shift registers which allows you to shift data in or out serially, and latch parallel data or set the outputs for the ram to read or write. All done with 5 pins, not much of a savings until you consider you can share every pin as an SPI bus. Since these memory operations are synchronous, you can use the cs on different pins, everything else can share the rest of the bus.
This is still a work in progress for this part so I havent considered what passive components to use for noise isolation or other things. What I am thinking through now is how to tie the ram read with the shift out, and ram write with the shift in.
More to come.